1. Field of the Invention
The present invention generally relates to a method of designing an integrated circuit having latches and more particularly to a method which eliminates redundant latches by combining latches.
2. Description of the Related Art
Current designs consume a significant portion of their total power in the latches and clock tree. Designers require latches to hold the state of the design from cycle to cycle. While some clock gating has been added to the architecture, the sheer number of latches impact the area and the overall clock tree design. On the other hand, the actual use of particular latches on a cycle by cycle basis is often sparse. In addition, whole cores of latches may be non-overlapping in a time domain. Unfortunately, designers are unable to effectively determine which latches are non-overlapping, especially, when often the overlapping latches are from diverse areas of the design and the designer may be unable to understand the uses of another designer's latch implementation.